A: What’s Going On In the Processors?
• Instruction completion counts
• Memory stall events
• Branches mispredicted
• Floating point instructions executed
• Floating mult-adds executed
• Branches executed
• Cycles
• Translation buffer misses
B: What’s Going On In the L1 Caches?
• Data cache misses
• Instruction cache misses
• Translation buffer misses
C: What’s Going On In the L2 Caches?
• Cacheable L2 requests from cores
• Write misses from DMA engine
• Read misses to DMA engine
• Misses from processor cores
• Accesses from processor cores
D: What’s Going On In the Central Switch?
• Read queue status from L2
• Write queue status from L2
• Read queue status from memory control
• Write queue status from memory control
E: What’s Going On In the Cache Coherence Logic?
• Misses in local L2
• Misses in all cores’ L2s
• Translation buffer misses
F: What’s Going On In the Memory Traffic?
• Reads issued to DIMM
• Writes issued to DIMM
• Sleep cycles
• Cycles with multiple requests in flight
G: What’s Going On In PCIexpress?
• Outbound memory transfers
• Inbound aligned reads
• Inbound unaligned reads
• Block reads
• Block writes
H: What’s Going On In the DMA Engine?
• DMA engine bus grants
• Microengine instructions executed
• Commands pending from user space
• Received blocks
• Transmitted blocks
I: What’s Going On In the Outgoing Fabric Links?
• Transmitted messages count
J: What’s Going On In the Incoming Fabric Links?
• Received messages count